GD32F450_BMC_BaseCode/app/bmc/main.h

#ifndef __MAIN_H__
#define __MAIN_H__

#include <stdint.h>
#include <pthread.h>
#include <unistd.h>
#include <sys/types.h>
#include <sys/stat.h>
#include <sys/socket.h>
#include "com_BmcType.h"
#include "com_IPMIDefs.h"
#include "BmcType.h"
#include "com_IPMI_SDRRecord.h"


#include "Session.h"
#include "sensor_tbl.h"
#include "MsgHndlr.h"
#include "hal_interface_api.h"
#include "com_BMCCfg.h"
/* Declare global variable */


/*---------------------------------------------------------------------------*
 * Interface SUPPORTED
 *---------------------------------------------------------------------------*/
#define LAN_IFC_SUPPORT					1
#define SERIAL_IFC_SUPPORT				0
#define SERIAL_TERMINAL_SUPPORT			0
#define SYS_IFC_SUPPORT					0
#define PRIMARY_IPMB_SUPPORT		1
#define SECONDARY_IPMB_SUPPORT		1
#define GROUP_EXTERN_SUPPORT		1
#define UDS_IFC_SUPPORT				1


#define PWR_CYCLE_INTERVAL			(3) 	//unit: 1s
#define REARM_SET_SENSOR_THRESHOLD	(0)		//whether rearm sensor event when change sensor threshold
#define CHASSIS_TIMER_INTERVAL		(1)		//1 second
#define FAN_CONTROL_INTERVAL		(5)		//5	second 
//IPMB
#define PRIMARY_IPMB_BUS			1	// /dev/i2c1
#define SECONDARY_IPMB_BUS			2	// /dev/i2c2
//#define PRIMARY_IPMB_ADDR			0x44
//#define SECONDARY_IPMB_ADDR			0x44

//RACK-ID
#define RACKID0_PORT	GPIOI
#define RACKID1_PORT	GPIOI
#define RACKID2_PORT	GPIOH
#define RACKID3_PORT	GPIOI
#define RACKID4_PORT	GPIOI
#define RACKID5_PORT	GPIOI
#define RACKID0_PIN		GPIO_PIN_6
#define RACKID1_PIN		GPIO_PIN_7
#define RACKID2_PIN		GPIO_PIN_15
#define RACKID3_PIN		GPIO_PIN_9
#define RACKID4_PIN		GPIO_PIN_10
#define RACKID5_PIN		GPIO_PIN_11

//SLOT-ID
#define GA0_PORT	GPIOH
#define GA1_PORT	GPIOH
#define GA2_PORT	GPIOH
#define GA3_PORT	GPIOH
#define GA4_PORT	GPIOH
#define GAP_PORT	GPIOI
#define GA0_PIN		GPIO_PIN_10
#define GA1_PIN		GPIO_PIN_11
#define GA2_PIN		GPIO_PIN_12
#define GA3_PIN		GPIO_PIN_13
#define GA4_PIN		GPIO_PIN_14
#define GAP_PIN		GPIO_PIN_5

#define GPIO1_PORT	GPIOC
#define GPIO2_PORT	GPIOC
#define GPIO3_PORT	GPIOD
#define GPIO4_PORT	GPIOD
#define GPIO5_PORT	GPIOD
#define GPIO6_PORT	GPIOE
#define GPIO7_PORT	GPIOE
#define GPIO8_PORT	GPIOE
#define GPIO1_PIN 	GPIO_PIN_12
#define GPIO2_PIN 	GPIO_PIN_13
#define GPIO3_PIN 	GPIO_PIN_2
#define GPIO4_PIN 	GPIO_PIN_3
#define GPIO5_PIN 	GPIO_PIN_6
#define GPIO6_PIN 	GPIO_PIN_2
#define GPIO7_PIN 	GPIO_PIN_3
#define GPIO8_PIN 	GPIO_PIN_4

extern sensor_tbl_t 				sensor_tbl[];
extern const OemFRUData_T 			Default_FRUData;
//extern OEM_SENSOR_CAPABILITY_T 		g_sensorList[SENSOR_NUMBERS];
extern const MgmtCtrlrDevLocator_T 	bmc_sdr;
extern const FullSensorRec_T 		full_sdr_tbl[];
extern const CompactSensorRec_T 	Compact_sdr_tbl[];

#define RESTORE_IPMI 	0x01
#define RESTORE_FRU		0x02
#define RESTORE_SDR		0x04
#define RESTORE_SEL		0x08
#define RESTORE_ALL		(RESTORE_IPMI | RESTORE_FRU | RESTORE_SDR | RESTORE_SEL)


extern pthread_t 	gThreadIDs[256];
extern uint8_t		gThreadIndex;

extern int gFd_LanIfcQ, gFd_LanResQ;
extern int gFdUdsIfc, gFdUdsRes;
extern int gFd_MsgHndlrIfc;
//extern int gFd_ChassisPwrHndlrQue;
extern int gFd_PrimaryIpmbIfcQ, gFd_PrimaryIpmbResQ;
extern int gFd_SecondaryIpmbIfcQ, gFd_SecondaryIpmbResQ;
extern int gPendActionIfc;
extern TLS_T g_tls;
extern PendingBridgedResTbl_T	m_PendingBridgedResTbl[MAX_PENDING_BRIDGE_TBL][MAX_PENDING_BRIDGE_RES];
extern PendingSeqNoTbl_T		m_PendingSeqNoTbl[16][MAX_PENDING_SEQ_NO];
//extern KCSBridgeResInfo_T       m_KCSBridgeResInfo;
extern TimerTaskTbl_T    		m_TimerTaskTbl [20];

extern BMCInfo_t 			g_BMCInfo;
extern SensorHistoryInfo_T 	gSensorHistoryInfo[SENSOR_NUMBERS];
extern FanInfo_T			gFanInfo[FAN_NUMBERS];
extern BladeStatus_T 		gBladeStatus[BLADE_NUMBERS];
extern uint8_t 				gChassisIPMBAddr[BLADE_NUMBERS];

#endif /* __MAIN_H__ */