hal_spi_interface.c 13 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650
  1. #include "driver.h"
  2. #include <linux/types.h>
  3. #include <stdio.h>
  4. #include <string.h>
  5. #include "com_gpio.h"
  6. #include "hal_interface_api.h"
  7. #include "linux/fcntl.h"
  8. #include "time.h"
  9. #include <unistd.h>
  10. #define DEV_NAME "/dev/spi"
  11. /*
  12. bus: 1,2,3,4,5,6
  13. */
  14. int stm32_spi_master_write(uint8_t spi, uint8_t *pBuf, uint32_t size)
  15. {
  16. int fd;
  17. int ret;
  18. uint8_t dev_name[10] = {0};
  19. spi_arg_t spi_arg;
  20. // GPIO_TypeDef *NSS_PORT = NULL;
  21. // uint16_t NSS_PIN = 0;
  22. switch(spi)
  23. {
  24. case 1:
  25. break;
  26. case 2:
  27. // NSS_PORT = GPIOI;
  28. // NSS_PIN = GPIO_PIN_0;
  29. break;
  30. case 3:
  31. break;
  32. case 4:
  33. break;
  34. case 5:
  35. // NSS_PORT = GPIOF;
  36. // NSS_PIN = GPIO_PIN_6;
  37. break;
  38. case 6:
  39. break;
  40. default:
  41. printf("Invalid bus number %d\n", spi);
  42. return -1;
  43. }
  44. sprintf(dev_name, "%s%d", DEV_NAME, spi);
  45. fd = open(dev_name, O_RDWR);
  46. if(fd == -1)
  47. {
  48. printf("Open %s failed!\n", dev_name);
  49. }
  50. // //NSS low
  51. // stm32_gpio_write(GPIOF, GPIO_PIN_6, GPIO_PIN_RESET);
  52. // usleep(1000);
  53. spi_arg.Size = size;
  54. memcpy(spi_arg.buf, pBuf, size);
  55. ret = ioctl(fd, SPI_MASTER_TRANSFER, &spi_arg);
  56. if(ret == -1)
  57. {
  58. printf("Write spi failed!\n");
  59. }
  60. // //NSS high
  61. // stm32_gpio_write(GPIOF, GPIO_PIN_6, GPIO_PIN_SET);
  62. close(fd);
  63. return 0;
  64. }
  65. int stm32_spi_master_read(uint8_t spi, uint8_t *pBuf, uint32_t size)
  66. {
  67. int fd;
  68. int ret;
  69. uint8_t dev_name[10] = {0};
  70. spi_arg_t spi_arg;
  71. // GPIO_TypeDef *NSS_PORT = NULL;
  72. // uint16_t NSS_PIN = 0;
  73. switch(spi)
  74. {
  75. case 1:
  76. break;
  77. case 2:
  78. // NSS_PORT = GPIOI;
  79. // NSS_PIN = GPIO_PIN_0;
  80. break;
  81. case 3:
  82. break;
  83. case 4:
  84. break;
  85. case 5:
  86. // NSS_PORT = GPIOF;
  87. // NSS_PIN = GPIO_PIN_6;
  88. break;
  89. case 6:
  90. break;
  91. default:
  92. printf("Invalid bus number %d\n", spi);
  93. return -1;
  94. }
  95. sprintf(dev_name, "%s%d", DEV_NAME, spi);
  96. fd = open(dev_name, O_RDWR);
  97. if(fd == -1)
  98. {
  99. printf("Open %s failed!\n", DEV_NAME);
  100. }
  101. spi_arg.Size = size;
  102. ret = ioctl(fd, SPI_MASTER_RECEIVE, &spi_arg);
  103. if(ret == -1)
  104. {
  105. printf("Read spi failed!\n");
  106. }
  107. memcpy(pBuf, spi_arg.buf, size);
  108. close(fd);
  109. return 0;
  110. }
  111. int stm32_spi_master_write_read(uint8_t spi, uint8_t *txBuf, uint32_t txSize, uint8_t *rxBuf, uint32_t rxSize)
  112. {
  113. int fd;
  114. int ret;
  115. uint8_t dev_name[10] = {0};
  116. spi_arg_t spi_arg;
  117. // GPIO_TypeDef *NSS_PORT = NULL;
  118. // uint16_t NSS_PIN = 0;
  119. switch(spi)
  120. {
  121. case 1:
  122. break;
  123. case 2:
  124. // NSS_PORT = GPIOI;
  125. // NSS_PIN = GPIO_PIN_0;
  126. break;
  127. case 3:
  128. break;
  129. case 4:
  130. break;
  131. case 5:
  132. // NSS_PORT = GPIOF;
  133. // NSS_PIN = GPIO_PIN_6;
  134. break;
  135. case 6:
  136. break;
  137. default:
  138. printf("Invalid bus number %d\n", spi);
  139. return -1;
  140. }
  141. sprintf(dev_name, "%s%d", DEV_NAME, spi);
  142. fd = open(dev_name, O_RDWR);
  143. if(fd == -1)
  144. {
  145. printf("Open %s failed!\n", DEV_NAME);
  146. }
  147. //Tx
  148. if(txSize > 0)
  149. {
  150. spi_arg.Size = txSize;
  151. memcpy(spi_arg.buf, txBuf, txSize);
  152. ret = ioctl(fd, SPI_MASTER_TRANSFER, &spi_arg);
  153. if(ret == -1)
  154. {
  155. printf("Read spi failed!\n");
  156. }
  157. }
  158. //Rx
  159. if(rxSize > 0)
  160. {
  161. spi_arg.Size = rxSize;
  162. memset(spi_arg.buf, 0, rxSize);
  163. ret = ioctl(fd, SPI_MASTER_RECEIVE, &spi_arg);
  164. if(ret == -1)
  165. {
  166. printf("Read spi failed!\n");
  167. }
  168. memcpy(rxBuf, spi_arg.buf, rxSize);
  169. }
  170. close(fd);
  171. return 0;
  172. }
  173. /*
  174. timeout: ms
  175. */
  176. static int sf_wait_spi_ready(int fd, uint32_t timeout)
  177. {
  178. spi_arg_t spi_arg;
  179. int ret = 0;
  180. uint32_t timeCnt = 0;
  181. spi_arg.Size = 1;
  182. spi_arg.buf[0] = 0x05;
  183. ret = ioctl(fd, SPI_MASTER_TRANSFER, &spi_arg);
  184. if(ret == -1)
  185. {
  186. printf("SPI Read status1 failed!\n");
  187. return -1;
  188. }
  189. timeCnt = 0;
  190. do{
  191. timeCnt++;
  192. spi_arg.Size = 1;
  193. ret = ioctl(fd, SPI_MASTER_RECEIVE, &spi_arg);
  194. if(ret == -1)
  195. {
  196. printf("SPI Read status1 failed!\n");
  197. }
  198. if(spi_arg.buf[0]&0x01)
  199. usleep(10);
  200. else
  201. break;
  202. }while(timeCnt < timeout*100);
  203. //NSS high
  204. //stm32_gpio_write(NSS_PORT, NSS_PIN, GPIO_PIN_SET);
  205. }
  206. /*
  207. flash: fw flash, spi5
  208. cmd: erase 4 KB
  209. */
  210. int sf_sector_erase(uint8_t spi, uint32_t offset)
  211. {
  212. int fd;
  213. int ret;
  214. uint8_t dev_name[10] = {0};
  215. spi_arg_t spi_arg;
  216. uint32_t erase_addr = 0;
  217. uint8_t status1_reg;
  218. uint32_t timeout = 0;
  219. GPIO_TypeDef *NSS_PORT = NULL;
  220. uint16_t NSS_PIN = 0;
  221. //erase_addr is the start address of one sector.
  222. erase_addr = (offset/4096)*4096;
  223. switch(spi)
  224. {
  225. case 1:
  226. break;
  227. case 2:
  228. NSS_PORT = GPIOI;
  229. NSS_PIN = GPIO_PIN_0;
  230. break;
  231. case 3:
  232. break;
  233. case 4:
  234. break;
  235. case 5:
  236. NSS_PORT = GPIOF;
  237. NSS_PIN = GPIO_PIN_6;
  238. break;
  239. case 6:
  240. break;
  241. default:
  242. printf("Invalid bus number %d\n", spi);
  243. return -1;
  244. }
  245. sprintf(dev_name, "%s%d", DEV_NAME, spi);
  246. fd = open(dev_name, O_RDWR);
  247. if(fd == -1)
  248. {
  249. printf("Open %s failed!\n", dev_name);
  250. }
  251. //Write Enable
  252. spi_arg.Size = 1;
  253. spi_arg.buf[0] = 0x06;
  254. stm32_gpio_write(NSS_PORT, NSS_PIN, GPIO_PIN_RESET); //NSS low
  255. ret = ioctl(fd, SPI_MASTER_TRANSFER, &spi_arg);
  256. stm32_gpio_write(NSS_PORT, NSS_PIN, GPIO_PIN_SET); //NSS high
  257. if(ret == -1)
  258. {
  259. printf("SPI Write Enable failed!\n");
  260. return -1;
  261. }
  262. //Sector Erase
  263. spi_arg.Size = 4;
  264. spi_arg.buf[0] = 0x20;
  265. spi_arg.buf[1] = (erase_addr>>16)&0xff;
  266. spi_arg.buf[2] = (erase_addr>>8)&0xff;
  267. spi_arg.buf[3] = erase_addr&0xff;
  268. stm32_gpio_write(NSS_PORT, NSS_PIN, GPIO_PIN_RESET); //NSS low
  269. ret = ioctl(fd, SPI_MASTER_TRANSFER, &spi_arg);
  270. stm32_gpio_write(NSS_PORT, NSS_PIN, GPIO_PIN_SET); //NSS high
  271. if(ret == -1)
  272. {
  273. printf("SPI sector erase failed!\n");
  274. return -1;
  275. }
  276. usleep(30000); //30ms
  277. stm32_gpio_write(NSS_PORT, NSS_PIN, GPIO_PIN_RESET); //NSS low
  278. sf_wait_spi_ready(fd, 400); //400ms
  279. stm32_gpio_write(NSS_PORT, NSS_PIN, GPIO_PIN_SET); //NSS high
  280. close(fd);
  281. return 0;
  282. }
  283. int sf_get_id(uint8_t spi, uint8_t *id)
  284. {
  285. int fd;
  286. spi_arg_t args;
  287. uint8_t dev_name[10] = {0};
  288. int i;
  289. GPIO_TypeDef *NSS_PORT = NULL;
  290. uint16_t NSS_PIN = 0;
  291. switch(spi)
  292. {
  293. case 1:
  294. break;
  295. case 2:
  296. NSS_PORT = GPIOI;
  297. NSS_PIN = GPIO_PIN_0;
  298. break;
  299. case 3:
  300. break;
  301. case 4:
  302. break;
  303. case 5:
  304. NSS_PORT = GPIOF;
  305. NSS_PIN = GPIO_PIN_6;
  306. break;
  307. case 6:
  308. break;
  309. default:
  310. printf("Invalid bus number %d\n", spi);
  311. return -1;
  312. }
  313. sprintf(dev_name, "%s%d", DEV_NAME, spi);
  314. fd = open(dev_name, O_RDWR);
  315. if(fd < 0)
  316. printf("open failed\n");
  317. memset(args.buf, 0, 100);
  318. args.buf[0] = 0x9f;
  319. args.Size = 1;
  320. stm32_gpio_write(NSS_PORT, NSS_PIN, GPIO_PIN_RESET); //NSS low
  321. ioctl(fd, SPI_MASTER_TRANSFER, &args);
  322. args.Size = 3;
  323. ioctl(fd, SPI_MASTER_RECEIVE, &args);
  324. stm32_gpio_write(NSS_PORT, NSS_PIN, GPIO_PIN_SET); //NSS high
  325. memcpy(id, args.buf, args.Size);
  326. //printf("get id: %#x %#x %#x\n", id[0], id[1], id[2]);
  327. close(fd);
  328. }
  329. /*
  330. spi: 1,2,3,4,5,6
  331. PageSize = 256 bytes.
  332. Address must be the start of one page.
  333. */
  334. int sf_write(uint8_t spi, uint32_t offset, uint8_t *buf, uint32_t size)
  335. {
  336. int fd;
  337. int ret;
  338. spi_arg_t spi_arg;
  339. uint8_t dev_name[10] = {0};
  340. uint8_t status1_reg;
  341. uint32_t timeout = 0;
  342. uint32_t remain = 0, writeLen = 0;
  343. uint32_t writeAddr = 0;
  344. GPIO_TypeDef *NSS_PORT = NULL;
  345. uint16_t NSS_PIN = 0;
  346. //erase_addr is the start address of one sector.
  347. if(offset&0xff)
  348. {
  349. printf("The Address %#x is not a pages start!\n", offset);
  350. return -1;
  351. }
  352. switch(spi)
  353. {
  354. case 1:
  355. break;
  356. case 2:
  357. NSS_PORT = GPIOI;
  358. NSS_PIN = GPIO_PIN_0;
  359. break;
  360. case 3:
  361. break;
  362. case 4:
  363. break;
  364. case 5:
  365. NSS_PORT = GPIOF;
  366. NSS_PIN = GPIO_PIN_6;
  367. break;
  368. case 6:
  369. break;
  370. default:
  371. printf("Invalid bus number %d\n", spi);
  372. return -1;
  373. }
  374. sprintf(dev_name, "%s%d", DEV_NAME, spi);
  375. fd = open(dev_name, O_RDWR);
  376. if(fd == -1)
  377. {
  378. printf("Open %s failed!\n", dev_name);
  379. }
  380. //usleep(1000);
  381. remain = size;
  382. writeLen = 0;
  383. writeAddr = offset;
  384. while(remain > 256)
  385. {
  386. //Write Enable
  387. spi_arg.Size = 1;
  388. spi_arg.buf[0] = 0x06;
  389. stm32_gpio_write(NSS_PORT, NSS_PIN, GPIO_PIN_RESET); //NSS low
  390. ret = ioctl(fd, SPI_MASTER_TRANSFER, &spi_arg);
  391. stm32_gpio_write(NSS_PORT, NSS_PIN, GPIO_PIN_SET); //NSS high
  392. if(ret == -1)
  393. {
  394. printf("SPI Write Enable failed!\n");
  395. return -1;
  396. }
  397. //Page Write
  398. spi_arg.Size = 260;
  399. spi_arg.buf[0] = 0x02; //page write
  400. spi_arg.buf[1] = (writeAddr>>16)&0xff;
  401. spi_arg.buf[2] = (writeAddr>>8)&0xff;
  402. spi_arg.buf[3] = writeAddr&0xff;
  403. memcpy(&spi_arg.buf[4], &buf[writeLen], 256);
  404. stm32_gpio_write(NSS_PORT, NSS_PIN, GPIO_PIN_RESET); //NSS low
  405. ret = ioctl(fd, SPI_MASTER_TRANSFER, &spi_arg);
  406. stm32_gpio_write(NSS_PORT, NSS_PIN, GPIO_PIN_SET); //NSS high
  407. if(ret == -1)
  408. {
  409. printf("SPI Read status1 failed!\n");
  410. return -1;
  411. }
  412. //wait page write finish
  413. usleep(700); //700us
  414. stm32_gpio_write(NSS_PORT, NSS_PIN, GPIO_PIN_RESET); //NSS low
  415. if(0 != sf_wait_spi_ready(fd, 3)) //3ms
  416. printf("Warnning page write timeout!\n");
  417. stm32_gpio_write(NSS_PORT, NSS_PIN, GPIO_PIN_SET); //NSS high
  418. remain -= 256;
  419. writeLen += 256;
  420. writeAddr += 256;
  421. }
  422. if(remain > 0)
  423. {
  424. //Write Enable
  425. spi_arg.Size = 1;
  426. spi_arg.buf[0] = 0x06;
  427. stm32_gpio_write(NSS_PORT, NSS_PIN, GPIO_PIN_RESET); //NSS low
  428. ret = ioctl(fd, SPI_MASTER_TRANSFER, &spi_arg);
  429. stm32_gpio_write(NSS_PORT, NSS_PIN, GPIO_PIN_SET); //NSS high
  430. if(ret == -1)
  431. {
  432. printf("SPI Write Enable failed!\n");
  433. return -1;
  434. }
  435. //page write
  436. spi_arg.Size = remain + 4;
  437. spi_arg.buf[0] = 0x02; //page write
  438. spi_arg.buf[1] = (writeAddr>>16)&0xff;
  439. spi_arg.buf[2] = (writeAddr>>8)&0xff;
  440. spi_arg.buf[3] = writeAddr&0xff;
  441. memcpy(&spi_arg.buf[4], &buf[writeLen], remain);
  442. stm32_gpio_write(NSS_PORT, NSS_PIN, GPIO_PIN_RESET); //NSS low
  443. ret = ioctl(fd, SPI_MASTER_TRANSFER, &spi_arg);
  444. stm32_gpio_write(NSS_PORT, NSS_PIN, GPIO_PIN_SET); //NSS high
  445. if(ret == -1)
  446. {
  447. printf("SPI Read status1 failed!\n");
  448. return -1;
  449. }
  450. //wait page write finish
  451. usleep(700); //700us
  452. stm32_gpio_write(NSS_PORT, NSS_PIN, GPIO_PIN_RESET); //NSS low
  453. if(0 != sf_wait_spi_ready(fd, 3)) //3ms
  454. printf("Warnning page write timeout!\n");
  455. stm32_gpio_write(NSS_PORT, NSS_PIN, GPIO_PIN_SET); //NSS high
  456. writeLen += remain;
  457. writeAddr += remain;
  458. remain -= remain;
  459. }
  460. close(fd);
  461. return 0;
  462. }
  463. /*
  464. spi: 1,2,3,4,5
  465. PageSize = 256 bytes.
  466. Address must be the start of one page.
  467. */
  468. int sf_read(uint8_t spi, uint32_t offset, uint8_t *buf, uint32_t size)
  469. {
  470. int fd;
  471. int ret;
  472. spi_arg_t spi_arg;
  473. uint8_t dev_name[10] = {0};
  474. uint8_t status1_reg;
  475. uint32_t timeout = 0;
  476. uint32_t remain = 0, readLen = 0;
  477. uint32_t readAddr;
  478. GPIO_TypeDef *NSS_PORT = NULL;
  479. uint16_t NSS_PIN = 0;
  480. //erase_addr is the start address of one sector.
  481. if(offset&0xff)
  482. {
  483. printf("The Address %#x is not a pages start!\n", offset);
  484. return -1;
  485. }
  486. switch(spi)
  487. {
  488. case 1:
  489. break;
  490. case 2:
  491. NSS_PORT = GPIOI;
  492. NSS_PIN = GPIO_PIN_0;
  493. break;
  494. case 3:
  495. break;
  496. case 4:
  497. break;
  498. case 5:
  499. NSS_PORT = GPIOF;
  500. NSS_PIN = GPIO_PIN_6;
  501. break;
  502. case 6:
  503. break;
  504. default:
  505. printf("Invalid bus number %d\n", spi);
  506. return -1;
  507. }
  508. sprintf(dev_name, "%s%d", DEV_NAME, spi);
  509. fd = open(dev_name, O_RDWR);
  510. if(fd == -1)
  511. {
  512. printf("Open %s failed!\n", dev_name);
  513. }
  514. remain = size;
  515. readLen = 0;
  516. readAddr = offset;
  517. while(remain > 256)
  518. {
  519. spi_arg.Size = 5;
  520. spi_arg.buf[0] = 0x0B; //fast read
  521. spi_arg.buf[1] = (readAddr>>16)&0xff;
  522. spi_arg.buf[2] = (readAddr>>8)&0xff;
  523. spi_arg.buf[3] = readAddr&0xff;
  524. spi_arg.buf[4] = 0; //dummy
  525. stm32_gpio_write(NSS_PORT, NSS_PIN, GPIO_PIN_RESET); //NSS low
  526. ret = ioctl(fd, SPI_MASTER_TRANSFER, &spi_arg);
  527. if(ret == -1)
  528. {
  529. printf("SPI Fast Read command failed!\n");
  530. return -1;
  531. }
  532. spi_arg.Size = 256;
  533. ret = ioctl(fd, SPI_MASTER_RECEIVE, &spi_arg);
  534. stm32_gpio_write(NSS_PORT, NSS_PIN, GPIO_PIN_SET); //NSS high
  535. if(ret == -1)
  536. {
  537. printf("SPI fast Read failed!\n");
  538. return -1;
  539. }
  540. memcpy(&buf[readLen], spi_arg.buf, 256);
  541. remain -= 256;
  542. readLen += 256;
  543. readAddr += 256;
  544. }
  545. if(remain > 0)
  546. {
  547. spi_arg.Size = 5;
  548. spi_arg.buf[0] = 0x0B; //fast read
  549. spi_arg.buf[1] = (readAddr>>16)&0xff;
  550. spi_arg.buf[2] = (readAddr>>8)&0xff;
  551. spi_arg.buf[3] = readAddr&0xff;
  552. spi_arg.buf[4] = 0; //dummy
  553. stm32_gpio_write(NSS_PORT, NSS_PIN, GPIO_PIN_RESET); //NSS low
  554. ret = ioctl(fd, SPI_MASTER_TRANSFER, &spi_arg);
  555. if(ret == -1)
  556. {
  557. printf("SPI Fast Read command failed!\n");
  558. return -1;
  559. }
  560. spi_arg.Size = remain;
  561. ret = ioctl(fd, SPI_MASTER_RECEIVE, &spi_arg);
  562. stm32_gpio_write(NSS_PORT, NSS_PIN, GPIO_PIN_SET); //NSS high
  563. if(ret == -1)
  564. {
  565. printf("SPI fast Read failed!\n");
  566. return -1;
  567. }
  568. memcpy(&buf[readLen], spi_arg.buf, remain);
  569. readLen += remain;
  570. readAddr += remain;
  571. remain -= remain;
  572. }
  573. close(fd);
  574. return 0;
  575. }